Semiconductor memory such as DRAM is constituted by three basic components: a memory cell array, an input/output buffer, and peripheral circuits interposed between the memory cell array and the input/output buffer. The power supply voltage supplied to the semiconductor memory is boosted or lowered before being supplied to each unit. Therefore transistors constituting each unit are configured so that they have appropriate oxide film thicknesses and threshold voltages (Vth) and that they have a predetermined breakdown voltage.
For instance, transistors having thick gate oxide films are used for the memory cell constituting DRAM because they need to have a high breakdown voltage. On the other hand, transistors having thin gate oxide films are used for the peripheral circuits while transistors having thick gate oxide films, as in the case with the memory cell, are used for the input/output buffer (refer to Patent Documents 1 and 2).
In the semiconductor memory configured as described, the thickness of the gate oxide films of the transistors used in the input/output buffer is the same as that of the gate oxide films of other transistors, therefore the manufacturing process can be simplified by using the same dopants for channel regions, resulting in the reduction of the manufacturing costs.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-11-297950
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2004-200714A